1. Field of the Invention
The present invention relates to a sigma-delta circuit and related method, and more particularly, to a sigma-delta circuit and related method with a time sharing architecture.
2. Description of the Prior Art
Recently, audio processing is implemented by general microprocessors such as central processing units (CPU) or digital signal processors (DSP). Another method for audio processing is implemented in field programmable gate arrays (FPGA), due to operational frequency of sigma-delta modulators being low enough to be implemented in FPGA easily. The sigma-delta modulators are already widespreadly applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC), because of the sigma-delta modulators having a capability of noise shaping to restrain quantized noise within signal bandwidths and to raise the signal to noise ratio further. Hence, the sigma-delta modulators are popular in application circuits with high resolution and middle (or low) speed.
Please refer to FIG. 1. FIG. 1 is a diagram of a first order sigma-delta modulator 10 in the prior art. The first order sigma-delta modulator 10 includes an adder 12, an integrator 13, a quantizer 14, a digital-to-analog converter 16, and a filter 18. Principles of the sigma-delta modulator 10 are rough estimating signals firstly to calculate errors, and then after integration, the errors are further compensated. As shown in FIG. 1, an input signal In1 and a feedback signal SFB of the digital-to-analog converter 16 are inputted into the adder 12 and are subtracted to generate an error signal Se. The error signal Se is integrated by the integrator 13 and then is quantized by the quantizer 14. Due to quantized errors resulting in noise being quantized, the noise should be filtered out by the filter 18 to finally output an output signal Out1.
Please refer to FIG. 2, which is a diagram of a second order sigma-delta modulator 20 in the prior art. The second order sigma-delta modulator 20 includes the adder 12, the integrator 13, a second adder 22, a second integrator 23, the quantizer 14, a digital-to-analog converter 16, and a filter 18. Orders of the sigma-delta modulator 20 depend on amount of feedback loops. As shown in FIG. 2, the input signal In1 and the feedback signal SFB of the digital-to-analog converter 16 are inputted into the adder 12 and are subtracted to generate the error signal Se. The error signal Se is integrated by the integrator 13 to generate an integration signal Si. The integration signal Si and the feedback signal SFB of the digital-to-analog converter 16 are inputted into the second adder 22 and are subtracted, and then are integrated by the second integrator 23 and are quantized by the quantizer 14. Due to quantized errors resulting in noise being quantized, the noise should be filtered out by the filter 18 to finally output the output signal Out1. Hence, the second order sigma-delta modulator 20 totally processes sigma-delta operations two times.
On this account, with the increasing of the orders of the sigma-delta operations, the circuit of the sigma-delta modulators becomes more and more complicated. Please refer to FIG. 3, which is a diagram of a fifth order sigma-delta modulator 30 in the prior art. As shown in FIG. 3, the fifth order sigma-delta operations are executed by a first sigma-delta processing element PE1, a second sigma-delta processing element PE2, a third sigma-delta processing element PE3, a fourth sigma-delta processing element PE4, and a fifth sigma-delta processing element PE5. Each sigma-delta processing element (PE1˜PE5) at least includes a multiplier, an adder, and an integrator. For example, the second sigma-delta processing element PE2 includes the multipliers a(2), b(2), g(1), and c(2), the integrator 332, and the adders 321 and 322. As shown in FIG. 3, a first order sigma-delta operation is processed on the input signal In1 by the first sigma-delta processing element PE1, and then a second, a third, a fourth, and a fifth order sigma-delta operations are processed on it sequentially. After finishing five orders of sigma-delta operations, the result is quantized by a quantizer 34 and then is delayed for a clock period by a delay unit 37 to finally output the output signal Out1. The five orders of the sigma-delta operations on the input signal In1 are obtained through the fifth order sigma-delta modulator 30. However, the fifth order sigma-delta modulator 30 needs at least eight adders, eighteen multipliers, and five integrators, which will waste hardware areas.
Direct implementations of audio processing will waste too much hardware areas and cost due to the audio processing only having frequencies of KHz. Hence, most designs are implemented by general microprocessors such as central processing units (CPU) or digital signal processors (DSP) recently, but their hardware cost is too high and will result in raising operational frequencies, which is difficult to be implemented in FPGA. In the prior art, sigma-delta circuits with multiple orders need a lot of adders, multipliers, and integrators. The more orders of the sigma-delta circuits that are used, the more adders, multipliers, and integrators are needed. These elements will increase not only manufacture cost but also hardware areas.